Lithography Limits: China's DUV Workarounds Face Rising Costs

Chinese semiconductor manufacturers face a significant strategic dilemma as they attempt to produce advanced processors without access to the industry's most critical equipment. Export controls have prevented the import of extreme ultraviolet lithography machines from ASML, the sole producer of these tools. Consequently, domestic firms must rely on older deep ultraviolet systems. While these machines can still fabricate high-performance silicon, the process requires multiple exposures per layer. This approach increases the likelihood of defects, extends production timelines, and significantly raises manufacturing costs, according to industry experts.

The lack of EUV capability has long been considered the primary obstacle for China's chip industry. ASML's equipment uses 13.5 nanometer wavelength light to print the finest features on modern processors. Analysts estimate that this technological gap places China at least five years behind Western competitors. Despite this disadvantage, Chinese firms have achieved progress that exceeds many initial expectations. A teardown of the Huawei Mate 60 Pro in 2023 revealed that its Kirin 9000S processor was manufactured by SMIC using a second-generation 7 nanometer class process without EUV. Recent analysis suggests SMIC has advanced its DUV-based process toward the density levels associated with 5 nanometer manufacturing, though it still lags behind the leading processes from TSMC and Samsung.

The key to this progress is multiple patterning. Instead of printing complex layers in a single step, manufacturers break the design into several simpler patterns and build the layer incrementally. Chris Mack, co-founder and CTO of Fractilia, noted that the feasibility of non-EUV chips depends on understanding these trade-offs. Industry standards previously suggested that three exposures on a 193 immersion tool cost roughly the same as one EUV exposure. However, when the process requires four masks, EUV becomes the more economical option.

Quality control presents another major challenge. Each new pattern must align precisely with previous etchings. Additional exposures lead to accumulated overlay errors and process variation. Designers can mitigate this by adding space around features, but this enlarges the chip and reduces the number of dies per wafer. Given that wafers cost tens of thousands of dollars, this reduction is financially significant. Mack emphasized that manufacturers sell dies, not wafers, making efficiency crucial.

Memory chip production highlights the efficiency gap. Morgan Stanley reported in June that Chinese DRAM maker CXMT produces only about one-third as many bits per wafer as its Western counterparts. The bank described lithography access as a hard ceiling for Chinese memory development. Mack also pointed out that process node labels like 5 nanometer or 3 nanometer have limited meaning in isolation. He noted that SMIC's N+3 process, while an improvement, remains significantly less scaled than established 5 nanometer processes from Samsung and TSMC.

DUV technology still has potential for further advancement. Micron developed its 1-alpha DRAM without EUV by using multiple patterning and tight process control. Mack stated that Micron pushed the 193 nanometer technology further than any other memory maker. Morgan Stanley believes CXMT's planned move to 1-alpha DRAM for HBM3e is achievable without EUV. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging to allow firms to use DUV for the latest DRAM generations by the end of the decade. Mack added that China could make substantial progress if it had the full 193 immersion ecosystem and designed products specifically for it, though he stressed that memory is easier to produce than logic chips.

Even Micron eventually adopted EUV for its 1-gamma DRAM, which offers more than 30 percent greater bit density per wafer than the previous 1-beta generation. EUV has its own drawbacks, such as stochastic effects that require higher exposure doses and increased costs. Nevertheless, Mack said he would be hard pressed to believe that 3 nanometer or 2 nanometer nodes could be economically viable without EUV.

Chinese chipmakers are unlikely to stall despite these challenges. They can continue pushing DUV technology while accepting larger dies, lower yields, or longer manufacturing times. They can also increase capacity. Morgan Stanley projects that CXMT will remain on 1-alpha without EUV but will increase its share of global DRAM bit supply from 14 percent in 2026 to 16 percent in 2028 through new greenfield capacity. The bank also expects China's AI chip self-sufficiency to rise from 42 percent in 2025 to 70 percent by 2030, even as gaps persist in EUV, HBM, and advanced software.